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System implications of LLC MSHRs in scalable memory systems

  • Published:2017-07 Issue: Volume:52 Page:355-364
  • ISSN:0141-9331
  • Container-title:Microprocessors and Microsystems
  • language:en
  • Short-container-title:Microprocessors and Microsystems

Author:

Marino Mario Donato,Li Kuan-ChingORCID

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference39 articles.

1. Micron Manufactures DRAM Components and Modules and NAND Flash, Accessed date: 11/28/2016; http://www.micron.com/.

2. ABat-FS: towards adjustable bandwidth and temperature via frequency scaling in scalable memory systems;Marino;Microprocess. Microsyst.,2016

3. RFiof: An RF approach to the I/O-pin and memory controller scalability for off-chip memories;Marino,2013

4. Corona: system implications of emerging nanophotonic technology;Vantrease,2008

5. The dimm tree architecture: a high bandwidth and scalable memory system;Therdsteerasukdi,2011

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1. Research on global register allocation for code containing array‐unit dual‐usage register names;Concurrency and Computation: Practice and Experience;2022-12-05

2. Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs;ACM Transactions on Reconfigurable Technology and Systems;2022-06-30

3. Stop Crying Over Your Cache Miss Rate;Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays;2019-02-20

4. Special issue on: ``Heterogeneous architectures for Cyber-physical systems (HACPS)'';Microprocessors and Microsystems;2017-07

5. WITHDRAWN: An investigative analysis of RFiop: RF-memory path to address on-package I/O pad and memory controller scalability;Journal of Computational Science;2017-03
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