Fast and accurate architectural vulnerability analysis for embedded processors using Instruction Vulnerability Factor-Reference-Cited by-同舟云学术

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Fast and accurate architectural vulnerability analysis for embedded processors using Instruction Vulnerability Factor

Published:2016-05 Issue: Volume:42 Page:113-126
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Azarpeyvand Ali,Salehi Mostafa E.,Fakhraie Seid Mehdi,Safari Saeed

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference61 articles.

1. Radiation-induced soft errors in advanced semiconductor technologies;Baumann;IEEE Trans. Device Mater. Reliab.,2005

2. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor;Mukherjee,2003

3. The soft error problem: An architectural perspective;Mukherjee,2005

4. Soft error sensitivity characterization for microprocessor dependability enhancement strategy;Kim,2002

5. Characterizing the effects of transient faults on a high-performance processor pipeline;Wang,2004

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1. An automated framework for selectively tolerating SDC errors based on rigorous instruction-level vulnerability assessment;Future Generation Computer Systems;2024-08

2. Estimating Code Vulnerability to Timing Errors via Microarchitecture-Aware Machine Learning;IEEE Design & Test;2021

3. Aging-Aware Instruction-Level Statistical Dynamic Timing Analysis for Embedded Processors;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2020-02

4. Instruction-Level NBTI Stress Estimation and Its Application in Runtime Aging Prediction for Embedded Processors;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-08

5. A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture;IEEE Computer Architecture Letters;2017-07-01

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