Modified single error correction orthogonal Latin square scheme to reduce parity check bits-Reference-Cited by-同舟云学术

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Modified single error correction orthogonal Latin square scheme to reduce parity check bits

Published:2022-10 Issue: Volume:94 Page:104676
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Ahmed Rabah Abood^ORCID

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference24 articles.

1. Multi-bit error tolerant caches using two-dimensional error coding;Kim,2007

2. Impact of intrinsic parameter fluctuation on the fault tolerance of L1 data cache;Ahmed,2009

3. Analyzing area and performance penalty of protecting different digital modules with hamming code and triple modular redundancy;Hentschke,2002

4. Error detecting and error correcting codes;Hamming;Bell Syst. Tech. J.,1950

5. Compact and power efficient SEC-DED codec for computer memory;Samanta;Microsyst. Technol.,2021

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Error Control Codes Based Modified Orthogonal Latin Squares for High-Speed Cache Memories;2023 IEEE 16th Dallas Circuits and Systems Conference (DCAS);2023-04-14

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