Variation aware power management for GPU memories

Author:

Maura Divyansh S.ORCID,Goel Tanmay,Goswami KaustavORCID,Banerjee Dip SankarORCID,Das Shirshendu

Funder

Ministry of Electronics and Information technology

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference44 articles.

1. Varius: A model of process variation and resulting timing errors for microarchitects;Sarangi;IEEE Trans. Semicond. Manuf.,2008

2. Harmonia: Balancing compute and memory power in high-performance gpus;Paul,2015

3. NVIDIA Ampere GA102 GPU Architecture Whitepaper, Tech. Rep., Santa Clara, CA, United States, 2020, https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.pdf, (Online).

4. Flipping bits in memory without accessing them: An experimental study of dram disturbance errors;Kim,2014

5. Revisiting rowhammer: An experimental analysis of modern dram devices and mitigation techniques;Kim,2020

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