Dynamic thread mapping for power-efficient many-core systems under performance constraints-Reference-Cited by-同舟云学术

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Dynamic thread mapping for power-efficient many-core systems under performance constraints

Published:2022-09 Issue: Volume:93 Page:104614
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Iskandar Veronia^ORCID,Salama Cherif^ORCID,Taher Mohamed^ORCID

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference58 articles.

1. Thousand core chips: A technology perspective;Borkar,2007

2. Big.little processing with ARM cortex-a15 & cortex-A7: Improving energy efficiency in high-performance mobile platforms;Greenhalgh,2011

3. Variable SMP–A Multi-Core CPU Architecture for Low Power and High Performance,2011

4. Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling;Semeraro,2002

5. Flicker: A dynamically adaptive architecture for power limited multicore systems;Petrica,2013

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Thermal Safe Power Constrained Dynamic Mapping for Heterogeneous Multicore System;Journal of Circuits, Systems and Computers;2024-06-01

2. Effect of Transient Failures on FPGA-based Heterogeneous Multicore System Scheduling;2022 4th Novel Intelligent and Leading Emerging Sciences Conference (NILES);2022-10-22

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