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An Architectural-Level Reliability Improvement Scheme in STT-MRAM Main Memory

  • Published:2022-04 Issue: Volume:90 Page:104462
  • ISSN:0141-9331
  • Container-title:Microprocessors and Microsystems
  • language:en
  • Short-container-title:Microprocessors and Microsystems

Author:

Mahdavi Nooshin,Razaghian Farhad,Farbeh Hamed

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference58 articles.

1. An analytical model for performance and lifetime estimation of hybrid DRAM-NVM main memories;Salkhordeh;IEEE Transactions on Computers,2019

2. Writeback-aware LLC management for PCM-based main memory systems;Pourshirazi;ACM Transactions on Design Automation of Electronic Systems (TODAES),2019

3. A Survey of Non-Volatile Main Memory Technologies: State-of-the-Arts, Practices, and Future Directions;Liu;Journal of Computer Science and Technology,2021

4. Revisiting rowhammer: An experimental analysis of modern dram devices and mitigation techniques;Kim,2020

5. CACF: A novel circuit architecture co-optimization framework for improving performance, reliability and energy of ReRAM-based main memory system;Zhang;ACM Transactions on Architecture and Code Optimization (TACO),2018

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1. TiCoSb Heusler alloy-based magnetic tunnel junction for efficient computing in memory architecture;Journal of Computational Electronics;2024-08-30

2. A high‐capacity and nonvolatile spintronic associative memory hardware accelerator;IET Circuits, Devices & Systems;2023-06-21

3. Gray counters for non-volatile memories;Memories - Materials, Devices, Circuits and Systems;2022-10

4. SOT-MRAM Based Main Memory: An Alternative to DRAM;2022 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT);2022-07-08
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