Functional self-test of high-performance pipe-lined signal processing architectures-Reference-Cited by-同舟云学术

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Functional self-test of high-performance pipe-lined signal processing architectures

Published:2015-11 Issue:8 Volume:39 Page:909-918
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Gorev Maksim,Ubar Raimund,Ellervee Peeter,Devadze Sergei,Raik Jaan,Min Mart

Funder

European Structural and Regional Development Funds

Estonian Doctoral School in Information and Communication Technology

IT Academy Program of Information Technology Foundation for Education

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference30 articles.

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2. L. Bushard, N. Chelstrom, S. Ferguson, B. Keller. DFT of the cell processor and its impact on EDA test software, in: IEEE Asian Test Symposium, 2006, pp. 369–374.

3. S. Wang, S. Gupta, ATPG for heat dissipation minimization during scan testing, in: ACM IEEE Design Automation Conference, 1997, pp. 614–619.

4. L. Chen, S. Ravi, A. Raghunathan, S. Dey, A scalable software-based self-test methodology for programmable processors, in: IEEE/ACM Design Automation Conference, 2003, pp. 548–553.

5. VLSI Test Principles and Architectures;Wang,2006

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