A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain with Carry-Save format numbers

Author:

Huang Yanxiang,Kapoor Ajay,Rutten Robert,Pineda de Gyvez José

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference22 articles.

1. Multirate digital filters, filter banks, polyphase networks, and applications: a tutorial;Vaidyanathan;Proc. IEEE,1990

2. Optimizing multistage decimation and interpolation processing;Coffey,2003

3. R. Zimmermann, D.Q. Tran, Optimized synthesis of sum-of-products, in: Signals, Systems and Computers. Conference Record of the Thirty-Seventh Asilomar Conference on, vol. 1, 2004, pp. 867-872.

4. D. Bekiaris, I. Sideris, G. Economakos, K.Z. Pekmestzi, Power-efficient and low latency implementation of programmable FIR filters using carry-save arithmetic, in: Electronics, Circuits and Systems. ICECS 2007. 14th IEEE International Conference on, 2007, pp. 1027–1030.

5. O. Gustafsson, A.G. Dempster, L. Wanhammar, Multiplier blocks using carry-save adders, in: Circuits and Systems. ISCAS ’04. Proceedings of the 2004 International Symposium on, vol. 2, 2004, pp. II-473-6.

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1. An Area-Efficient Column-Parallel Digital Decimation Filter With Pre-BWI Topology for CMOS Image Sensor;IEEE Transactions on Circuits and Systems I: Regular Papers;2018-08

2. Implementation Studies of Multi-rate Systems;Advances in Multirate Systems;2017-09-10

3. Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters;IEEE Transactions on Circuits and Systems I: Regular Papers;2017-09

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