1. Expression-tree based algorithms for code compression on embedded RISC architectures;Araújo;IEEE Trans. VLSI Syst.,2000
2. A VLIW architecture for a trace scheduling compiler;Colwell;IEEE Trans. Comput.,1988
3. J. Heikkinen, A. Cilio, J. Takala, H. Corporaal, Dictionary-based program compression on transport triggered architectures, in: Proceedings of the IEEE International Symposium on Circuits and Systems, Kobe, Japan, 2005, pp. 1122–1125.
4. J. Heikkinen, J. Takala, H. Corporaal, Dictionary-based program compression on TTAs: Effects on area and power consumption, in: Proceedings of the IEEE Workshop on Sig. Proc. Systems, Athens, Greece, 2005, pp. 479–484.
5. J. Heikkinen, J. Takala, Effects of program compression, in: Accepted to Proc. Embedded Comput. Syst.: Architectures, Modeling, and Simulation, Samos, Greece, 2006.