Bit Impact Factor: Towards making fair vulnerability comparison

Author:

Can Serdar Zafer,Yalcin Gulay,Ergin Oguz,Unsal Osman Sabri,Cristal Adrian

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference24 articles.

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3. Designing reliable systems from unreliable components: the challenges of transistor variability and degradation;Borkar;IEEE Micro,2005

4. S.S. Mukherjee, C. Weaver, J. Emer, S.K. Reinhardt, T. Austin, A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor, in: Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003, pp. 29–41.

5. X. Li, S.V. Adve, P. Bose, J.A. Rivers, Architecture-level soft error analysis: examining the limits of common assumptions, in: Proceedings of International Conference on Dependable Systems and Networks, 2007, pp. 266–275.

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2. ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph;2021 IEEE International Test Conference (ITC);2021-10

3. A Survey of Techniques for Modeling and Improving Reliability of Computing Systems;IEEE Transactions on Parallel and Distributed Systems;2016-04-01

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