1. G. Fey, A. Bernasconi, V. Ciriani, R. Drechsler, On the construction of mall fully testable circuits with low depth, in: EUROMICRO Symposium on Digital System Design, 2007, pp. 563–569.
2. Multiple-valued minimization for PLA optimization;Rudell;IEEE Transactions on CAD of Integrated Circuits and Systems CAD-6,1987
3. Synthesis of fully testable circuits from BDDs;Drechsler;IEEE Transactions on CAD,2004
4. D. Debnath, T. Sasao, Multiple–valued minimization to optimize PLAs with output EXOR gates, in: IEEE International Symposium on Multiple-Valued Logic, 1999, pp. 99–104.
5. E. Dubrova, D. Miller, J. Muzio, AOXMIN-MV: A heuristic algorithm for AND-OR-XOR minimization, in: Fourth International Workshop on the Applications of the Reed Muller Expansion in Circuit Design, 1999, pp. 37–54.