On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology-Reference-Cited by-同舟云学术

On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology

Published:2008-08 Issue:5-6 Volume:32 Page:244-253
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Roberts David,Kim Nam Sung,Mudge Trevor

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference19 articles.

1. A process-tolerant cache architecture for improved yield in nanoscale technologies;Agarwal;IEEE Trans. VLSI Syst.,2005

2. Leakage current – Moore’s law meets static power;Kim;IEEE Comput.,2003

3. M. Agostinelli, Erratic fluctuations of SRAM cache Vmin at the 90nm process technology node, in: IEEE International Electron Devices Meeting (IEDM), December 2005, pp. 655–658.

4. Performance implications of tolerating cache faults;Pour;IEEE Trans. Comput.,1993

5. Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS;Mukhopadhyay;IEEE Trans. CAD,2005

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1. Energy efficiency in multicore shared cache by fault tolerance using a genetic algorithm based block reuse predictor;Microprocessors and Microsystems;2023-09

2. Research and Implement of Cache Fault Tolerance Technique;Journal of Physics: Conference Series;2019-06-01

3. A Survey of Architectural Techniques for Near-Threshold Computing;ACM Journal on Emerging Technologies in Computing Systems;2016-07-26

4. Cluster Cache Monitor: Leveraging the Proximity Data in CMP;International Journal of Parallel Programming;2014-11-04

5. The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults;2012 45th Annual IEEE/ACM International Symposium on Microarchitecture;2012-12