Funder
Fundação de Amparo à Pesquisa do Estado de São Paulo
Subject
Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software
Reference37 articles.
1. Divide and conquer high-level synthesis design space exploration;Schafer;ACM Trans. Des. Autom. Electron. Syst.,2012
2. A performance analysis framework for optimizing opencl applications on FPGAs;Wang,2016
3. Probabilistic multiknob high-level synthesis design space exploration acceleration;Schafer;IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.,2016
4. A. Canis, S.D. Brown, J.H. Anderson, 2014. Modulo SDC scheduling with recurrence minimization in high-level synthesis, in: 2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014, pp. 1–8, doi:10.1109/FPL.2014.6927490.
5. SDC-Based modulo scheduling for pipeline synthesis;Zhang,2013