Efficient majority logic magnitude comparator design

Author:

Efstathiou Constantinos,Kitsos Paris

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference31 articles.

1. Computer Architecture a Quantitative Approach;Hennessy,2012

2. CMOS VLSI design: A Circuits and Systems Perspective;Weste,2011

3. Design and implementation of compression algorithm comparator for digital image processing on component;Sheng,2008

4. Limits to binary logic switch scaling-a gedanken model;Zhimov;Proceedings of the IEEE,2003

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1. Design and Analysis of CNTFET based Dynamic Comparator;2023 4th International Conference on Electronics and Sustainable Communication Systems (ICESC);2023-07-06

2. Design and Optimization of 4-bit Absolute-value Detector Based on CMOS;Journal of Physics: Conference Series;2023-02-01

3. Majority Logic Based In-Memory Comparator;2022 IEEE International Conference on Semiconductor Electronics (ICSE);2022-08-15

4. Novel optimized ultra-dense 1-bit magnitude comparator design in quantum-dot cellular automata technology based on MV32 gate;The Journal of Supercomputing;2022-06-11

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