A directional and scalable streaming deblocking filter hardware architecture for HEVC decoder

Author:

Baldev Swamy,Rathore Pradeep Kumar,Peesapati RangababuORCID,Anumandla Kiran Kumar

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference17 articles.

1. HEVC complexity and implementation analysis;Bossen;IEEE Trans. Circuits Syst. Video Technol.,2012

2. ITU-T, ISO/IEC, High Efficiency Video Coding,2013

3. A high performance deblocking filter hardware for high efficiency video coding;Ozcan;IEEE Trans. Consum. Electron.,2013

4. A high-throughput and multi-parallel VLSI architecture for HEVC deblocking filter;Zhou;IEEE Trans. Multimedia,2016

5. The VLSI architecture of a highly efficient deblocking filter for HEVC systems;Hsu;IEEE Trans. Circuits Syst. Video Technol.,2017

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