TileNET: Hardware accelerator for ternary Convolutional Neural Networks-Reference-Cited by-同舟云学术

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TileNET: Hardware accelerator for ternary Convolutional Neural Networks

Published:2021-06 Issue: Volume:83 Page:104039
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Eetha Sagar,P.K. Sruthi,Pant Vibha,Vikram Sai,Mody Mihir,Purnaprajna Madhura

Funder

Department of Science and Technology

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference29 articles.

1. In-datacenter performance analysis of a tensor processing unit;Jouppi,2017

2. J. Albericio, P. Judd, T. Hetherington, T. Aamodt, N.E. Jerger, A. Moshovos, Cnvlutin: Ineffectual-neuron-free deep neural network computing, in: 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), 2016, pp. 1–13.

3. Ternary weight networks;Li,2016

4. C. Farabet, B. Martini, B. Corda, P. Akselrod, E. Culurciello, Y. LeCun, NeuFlow: A runtime reconfigurable dataflow processor for vision, in: CVPR 2011 WORKSHOPS, 2011, pp. 109–116.

5. M. Peemen, A.A.A. Setio, B. Mesman, H. Corporaal, Memory-centric accelerator design for convolutional neural networks, in: 2013 IEEE 31st International Conference on Computer Design (ICCD), 2013, pp. 13–19.

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