Decimal addition on FPGA based on a mixed BCD/excess-6 representation-Reference-Cited by-同舟云学术

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Decimal addition on FPGA based on a mixed BCD/excess-6 representation

Published:2017-11 Issue: Volume:55 Page:91-99
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Neto Horácio,Véstias Mário

Funder

FCT

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference45 articles.

1. Decimal floating-point: algorism for computers;Cowlishaw,2003

2. A software implementation of the IEEE 754R decimal floating-point arithmetic using the binary encoding format;Cornea,2007

3. ANSI C decnumber library v3.68., Feb. (2012), [Online]. Available: http://speleotrove.com/decimal/decNumber.html.

4. GNU C compiler library. [Online]. Available: http://gcc.gnu.org/onlinedocs/gcc/Decimal-Float.html.

5. The IBM z900 decimal arithmetic unit;Busaba,2001

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1. Analysis and efficient implementation of IEEE-754 decimal floating point adders/subtractors in FPGAs for DPD and BID encoding;The Journal of Supercomputing;2023-12-06

2. Impact of Radix-10 Redundant Digit Set [−6, 9] on Basic Decimal Arithmetic Operations;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-01

3. Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor;Algorithms;2021-06-29

4. Design and implementation of modified BCD digit multiplier for digit-by-digit decimal multiplier;Analog Integrated Circuits and Signal Processing;2021-01-11

5. Improving the area of fast parallel decimal multipliers;Microprocessors and Microsystems;2018-09

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