Low power single precision BCD floating–point Vedic multiplier-Reference-Cited by-同舟云学术

Low power single precision BCD floating–point Vedic multiplier

Published:2020-02 Issue: Volume:72 Page:102930
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Ramya V.,Seshasayanan R.

Funder

Anna Centenary Research Fellowship

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference27 articles.

1. High-accuracy fixed-width modified Booth multipliers for lossy applications;Wang;IEEE Trans. Very Large Scale Integr. VLSI Syst.,2011

2. A new VLSI architecture of parallel multiplier–accumulator based on the Radix-2 modified Booth algorithm;Seo;IEEE Trans. Very Large Scale Integr. VLSI Syst.,2010

3. Design of approximate radix-4 Booth multipliers for error-tolerant computing;Liu;IEEE Trans. Comput.,2017

4. Comparative study of 16-order FIR filter design using different multiplication techniques;Mittal;IET Circ. Devices . Syst.,2017

5. The signed fixed-point multiplier for DSP using the vertically and crosswise algorithm;Ashwath,2013

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