Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment

Author:

Chen Yung-Yuan,Leu Kuen-Long

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference31 articles.

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2. P. Shivakumar et al., Modeling the effect of technology trends on the soft error rate of combinational logic, in: DSN’02, 2002, pp. 389–398.

3. Characterization of soft errors caused by single event upsets in CMOS processes;Karnik;IEEE Trans. Dependable Secure Comput.,2004

4. J.B. Nickle, A.K. Somani, REESE: a method of soft error detection in microprocessors, in: DSN’01, 2001, pp. 401–410.

5. D.M. Blough, A. Nicolau, Fault tolerance in super-scalar and vliw processors, in: IEEE Workshop on Fault Tolerant Parallel and Distributed Systems, 1992, pp. 193–200.

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1. Dynamic fault-tolerant VLIW processor with heterogeneous Function Units;Microprocessors and Microsystems;2022-09

2. Dynamic Trade-off among Fault Tolerance, Energy Consumption, and Performance on a Multiple-Issue VLIW Processor;IEEE Transactions on Multi-Scale Computing Systems;2018-07-01

3. Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors;ACM Journal on Emerging Technologies in Computing Systems;2017-03-10

4. A Novel Phase-Based Low Overhead Fault Tolerance Approach for VLIW Processors;2015 IEEE Computer Society Annual Symposium on VLSI;2015-07

5. Configurable Fault-Tolerance for a Configurable VLIW Processor;Lecture Notes in Computer Science;2013

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