Reduction methods for adapting optical network on chip topologies to 3D architectures-Reference-Cited by-同舟云学术

Reduction methods for adapting optical network on chip topologies to 3D architectures

Published:2013-02 Issue:1 Volume:37 Page:87-98
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Le Beux Sébastien,O’Connor Ian,Nicolescu Gabriela,Bois Guy,Paulin Pierre

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference23 articles.

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2. L. Zhang, M. Yang, Y. Jiang, E. Regentova, E. Lu, Generalized wavelength routed optical micronetwork in network-on-chip, in: Proc. 18th Int. Conf. Parallel and Distributed Computing and Systems (IASTED), Dallas, TX, November 2006, pp. 698–703.

3. Design, simulation, and characterization of a passive optical add-drop filter in silicon-on-insulator technology;Kazmierczak;IEEE Photon. Technol. Lett.,2005

4. A. Kazmierczak, et al., Design and characterisation of optical networks on chip, in: Proc. Eur. Conf. Integrated Optics (ECIO), Grenoble, France, April 2005.

5. M. Briere, E. Drouard, F. Mieyeville, D. Navarro, I. O’Connor, F. Gaffiot, Heterogeneous modelling of an Optical Network-on-Chip with SystemC, in: Proc. Rapid System Prototyping Workshop (RSP), June 2005.

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