1. Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study;Rebaudengo;IEEE Trans. Nucl. Sci.,2002
2. R. Velazco, F. Franco, Single event effects on digital integrated circuits: origins and mitigation techniques, in: IEEE International Symposium on Industrial Electronics, Vigo, Spain, June 2007.
3. J. Gaisler, A portable and fault-tolerant microprocessor based on the SPARC V8 architecture, in: International Conference on Dependable Systems and Networks, June 2002.
4. Software detection mechanisms providing full coverage against single bit-flip faults;Nicolescu;IEEE Trans. Nucl. Sci.,2004
5. M.S. Reorda, L. Sterpone, M. Violante, M. Garcia, C. Ongil, L. Entrena, Fault Injection-based reliability evaluation of SoPCs, in: 11th IEEE European Test Symposium, Southampton, UK, May 2006.