The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model-Reference-Cited by-同舟云学术

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The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model

Published:2008-10 Issue:7 Volume:32 Page:364-374
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Goudarzi Maziar,Hessabi Shaahin,MohammadZadeh Naser,Zainolabedini Nasim

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference36 articles.

1. International Technology Roadmap for Semiconductors (ITRS)-Design, 2005. Available at .

2. N. Flaherty, On a Higher Level, Report from the 41st Design Automation Conference, IEE Review, July 2004, pp. 22–24.

3. Formal Verification of Hardware Design;Yoeli,1990

4. Hardware Design Verification: Simulation and Formal Method-Based Approaches;Lam,2005

5. Digital Systems Testing and Testable Design;Abramovici,1995

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A systematic approach to configurable functional verification of HW IP blocks at transaction level;Computers & Electrical Engineering;2012-11

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