Exploration of a scalable and power-efficient asynchronous Network-on-Chip with dynamic resource allocation-Reference-Cited by-同舟云学术

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Exploration of a scalable and power-efficient asynchronous Network-on-Chip with dynamic resource allocation

Published:2018-07 Issue: Volume:60 Page:173-184
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Effiong Charles,Sassatelli Gilles,Gamatie Abdoulaye

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference36 articles.

1. Networks on chips: a new soc paradigm;Benini;Computer,2002

2. Deadlock-free message routing in multiprocessor interconnection networks;Dally;IEEE Trans. Comp.,1987

3. Thousand core chips: a technology perspective;Borkar,2007

4. Dlabs: a dual-lane buffer-sharing router architecture for networks on chip;Tran,2010

5. Leakage power modeling and optimization in interconnection networks;Chen,2003

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect;Micromachines;2022-12-17

2. Design and Implementation of High Performance 2D Mesh NoC Based On New Proposed Router Using FPGA;2021 7th International Conference on Contemporary Information Technology and Mathematics (ICCITM);2021-08-25

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