Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory-Reference-Cited by-同舟云学术

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Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory

Published:2013-08 Issue:7 Volume:59 Page:389-399
ISSN:1383-7621
Container-title:Journal of Systems Architecture
language:en
Short-container-title:Journal of Systems Architecture

Author:

Hu Jingtong,He Yi,Zhuge Qingfeng,Sha Edwin H.-M.,Xue Chun Jason,Zhao Yingchao

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference30 articles.

1. Available from: .

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4. Available from: .

5. A compiler approach to managing storage and memory bandwidth in configurable architectures;Baradaran;ACM Trans. Des. Autom. Electron. Syst.,2008

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