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Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications

  • Published:2007-10 Issue:10 Volume:53 Page:703-718
  • ISSN:1383-7621
  • Container-title:Journal of Systems Architecture
  • language:en
  • Short-container-title:Journal of Systems Architecture

Author:

Ohlendorf Rainer,Wild Thomas,Meitinger Michael,Rauchfuss Holm,Herkersdorf Andreas

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference17 articles.

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2. Beyond best effort: router architectures for the differentiated services of tomorrow’s internet;Kumar;IEEE Communications Magazine,1998

3. Evaluating Application-aware Firewall Performance, Agilent Technologies White Paper. , September 14, 2004.

4. N. Shah, Understanding Network Processors, in: Berkeley Technical Report, September 2001.

5. Intel IXP 2400 Network Processor, .

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1. Memory Architecture Quad Core Risc Processor on Altera FPGA De Nano Board;2015 Fifth International Conference on Communication Systems and Network Technologies;2015-04

2. Design and Implementation of a RISC Processor on FPGA;Advanced Materials Research;2014-07

3. Queueing model analysis and scheduling strategy for embedded multi-core SoC based on task priority;Computers & Electrical Engineering;2013-01

4. Instruction set architectural guidelines for embedded packet-processing engines;Journal of Systems Architecture;2012-03

5. FlexPath NP—Flexible, Dynamically Reconfigurable Processing Paths in Network Processors;Dynamically Reconfigurable Systems;2010
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