Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip

Author:

Harbin James,Soares Indrusiak Leandro

Funder

Engineering and Physical Sciences Research Council

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference32 articles.

1. Outstanding research problems in NoC design: System, microarchitecture, and circuit perspectives;Marculescu;IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.,2009

2. QNoC: QoS architecture and design process for network on chip;Bolotin;J. Syst. Archit.,2004

3. Transaction Level Modeling in System Level Design;Cai,2003

4. Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration;Indrusiak,2011

5. Fast transaction-level dynamic power consumption modelling in priority preemptive wormhole switching networks on chip;Harbin,2013

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