Optimal sample length for efficient cache simulation

Author:

Eeckhout Lieven,Niar Smaïl,De Bosschere Koen

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference19 articles.

1. Combining trace sampling with single pass methods for efficient cache simulation;Conte;IEEE Transactions on Computers,1998

2. T.M. Conte, M.A. Hirsch, K.N. Menezes, Reducing state loss for effective trace sampling of superscalar processors, in: Proceedings of the 1996 International Conference on Computer Design (ICCD-96), 1996, pp. 468–477.

3. P. Crowley, J.-L. Baer, Trace sampling for desktop applications on Windows NT, in: Proceedings of the First Workshop on Workload Characterization (WWC-1998) held in conjunction with the 31st ACM/IEEE Annual International Symposium on Microarchitecture (MICRO-31), 1998.

4. L. Eeckhout, S. Eyerman, B. Callens, K. De Bosschere, Accurately warmed-up trace samples for the evaluation of cache memories, in: Proceedings of the 2003 High Performance Computing Symposium (HPC-2003), 2003, pp. 267–274.

5. J.W. Haskins Jr., K. Skadron, Minimal subset evaluation: Rapid warm-up for simulated hardware state, in: Proceedings of the 2001 International Conference on Computer Design (ICCD-2001), 2001, pp. 32–39.

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. StatStack: Efficient modeling of LRU caches;2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS);2010-03

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