1. A design flow for configurable embedded processors based on optimized instruction set extension synthesis;Leupers,2006
2. Hardware/software instruction set configurability for system-on-chip processors;Wang,2001
3. Algorithms for the automatic extension of an instruction-set;Galuzzi,2009
4. Streaming FFT on REDEFINE-v2: an application architecture design space exploration;Fell,2009
5. Instruction generation and regularity extraction for reconfigurable processors;Brisk,2002