High-performance hard-input LDPC decoding on multi-core devices for optical space links-Reference-Cited by-同舟云学术

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High-performance hard-input LDPC decoding on multi-core devices for optical space links

Published:2023-04 Issue: Volume:137 Page:102832
ISSN:1383-7621
Container-title:Journal of Systems Architecture
language:en
Short-container-title:Journal of Systems Architecture

Author:

Le Gal Bertrand^ORCID,Jego Christophe,Pignoly Vincent

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference57 articles.

1. C. Marchand, E. Boutillon, LDPC decoder architecture for DVB-S2 and DVB-S2X standards, in: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS, Hangzhou, China, October, 2015.

2. V. Pignoly, et al., High data rate and flexible hardware QC-LDPC decoder for satellite optical communications, in: Proceedings of ISTC, 2018, pp. 1–5.

3. GPU-based DVB-S2 LDPC decoder with high throughput and fast error floor detection;Falcao;Electron. Lett.,2011

4. High-throughput multi-core LDPC decoders based on x86 processor;Le Gal;IEEE Trans. Parallel Distrib. Syst.,2016

5. B. Le Gal, C. Jego, Low-latency software LDPC decoders for x86 multi-core devices, in: Proceedings of SiPS, 2017.

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1. Comparing the Performance of the Latest Generation Multi-Threaded and Multi-Core ASICs;2024 International Conference on Optimization Computing and Wireless Communication (ICOCWC);2024-01-29

2. Evaluation of Dynamic Resource Allocation for Multi-Core ASICs;2024 International Conference on Optimization Computing and Wireless Communication (ICOCWC);2024-01-29

3. Low Power LDPC Decoding by Reliable Voltage Down-Scaling;2023 IEEE Nordic Circuits and Systems Conference (NorCAS);2023-10-31

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