A clocking technique for FPGA pipelined designs

Author:

Cadenas Oswaldo,Megson Graham

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference20 articles.

1. Designing for low power circuits: practical recipes;Benini;IEEE Circuits and Systems magazine,2001

2. F.C. Cheng. Practical design and performance evaluation of completion detection circuits, in: Int. Conf. on Computer Design, ICCD, October 1998

3. A. Davis, S. Nowick, An introduction to asynchronous system design, University of Utah, Report N. UUCS-97-013, Salt Lake City, 1997

4. Completion-detection carry select addition;Gloria;IEE Proceedings––Computer Digital Techniques,2000

5. S. Hauck, S. Burns, G. Borriello, C. Ebeling, Montage: an FPGA for synchronous and asynchronus circuits, in: 2nd Int. Workshop on Field-Programmable Gate Arrays, August 1992

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