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2. Power driven chaining of flip-flops in scan architectures;Bonhomme;Proceedings of IEEE test conference,2002
3. Test power: a big issue in large SOC designs;Bonhomme;IEEE International Workshop on Electronic design, test and applications,2002
4. C. Shi and R. Kapur, 2004. How Power Aware Test Improves Reliability and Yield, IEEDesign.com.
5. A Case Study of IR-Drop in Structured At-Speed Testing;Saxena;IEEE International Test Conference,2003