Secure Smart Card IP

Abstract

This book chapter highlights the embedded system security by designing a secure smart card IP. Indeed, the smart card is recognized as a privileged means of both storing confidential information and performing secure transactions. Its main role comes from the security it provides inside the system it is a part of. The specification and development of the elaborate smart card architecture are very delicate steps that require the pooling of strong competences in computer security, electronics, and also cryptography. The developed secure smart card IP model is based on the Gaisler LEON2 processor. To ensure a maximum level of security and optimal performance, a hardware integration of cryptographic mechanisms through instruction extensions was carried out. The integrated mechanisms allow for ensuring confidentiality, hashing, random number generation, and digital signature. The proposed smart card IP was implemented on a reconfigurable FPGA platform, and then on ASIC using 40 nm CMOS technology. A surface area of 1.08 mm2 with a consumed dynamic power of 23 mW for a frequency of 13.5 MHz was achieved.