Case Study: First-Time Success ASIC Design Methodology Applied to a Multi-Processor System-on-Chip

Author:

Wicaksana Arya,Kusuma Halim Dareen,Hartono Dicky,Lokananta Felix,Lee Sze-Wei,Ng Mow-Song,Tang Chong-Ming

Publisher

IntechOpen

Reference17 articles.

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2. ExtremeTech. What to Expect From Apple’s Neural Engine in the A11 Bionic SoC [Internet]. 2017. Available from: https://www.extremetech.com/mobile/255780-apple-neural-engine-a11-bionic-soc [Accessed: 2018-06-03]

3. Lusala AK, Manet P, Rousseau B, Legat JD. NoC implementation in FPGA using torus topology. In: 2007 International Conference on Field Programmable Logic and Applications. 2007

4. Kharchenko VA. Problems of reliability of electronic components. Modern Electronic Materials. 2015;1:88-92. DOI: 10.1016/j.moem.2016.03.002

5. Delta. SEM analysis reveals real cause of chip failure. Available from: https://asic.madebydelta.com/portfolio/sem-analysis-reveals-real-cause-of-chip-failure [Accessed: 2018-06-03]

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1. Lotus-G: The PVT TLM Virtual Platform for Early RUMPS401 Software Development;Lecture Notes in Electrical Engineering;2019-12-17

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