FPGA‐SRAM Soft Error Radiation Hardening
Author:
Publisher
InTech
Link
http://www.intechopen.com/download/pdf/53004
Reference22 articles.
1. Yamauchi, H. Embedded Memories for Nano-Scale VLSIs. Aurburn: Springer Publishing Company; 2009.
2. Yamauchi, H. Embedded SRAM circuit design technologies for a 45nm and beyond. In: 7th International Conference on ASIC; Guilin. IEEE Press; 2007. p. 1028–1033.
3. Pavlov, A.; Sachdev, M. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test. Auburn: Springer Publishing Company; 2008.
4. Normand, E. Single Event Effects in Avionics and on the Ground. International Journal of High Speed Electronics and Systems. 2004;14(2): 285–298.
5. Baumann, R. C. Soft errors in advanced semiconductor devices-part I: the three radiation sources. IEEE Transactions on Device and Materials Reliability. 2001;1(1):17–22.
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