Low-Power CMOS image sensor with multi-column-parallel SAR ADC-Reference-Cited by-同舟云学术

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Low-Power CMOS image sensor with multi-column-parallel SAR ADC

Published:2021-07-31 Issue:4 Volume:30 Page:223-228
ISSN:1225-5475
Container-title:JOURNAL OF SENSOR SCIENCE AND TECHNOLOGY
language:en
Short-container-title:KSS

Author:

Hyun Jang-Su,Kim Hyeon-June

Funder

Kangwon National University

National Research Foundation of Korea

Ministry of Science and ICT

Publisher

The Korean Sensors Society

Reference18 articles.

1. http://www.epnc.co.kr/news/articleView.html?idxno=75952/ (retrieved on Apr. 21, 2021).

2. Wireless Multimedia Cognitive Radio Networks: A Comprehensive Survey

3. 11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors

4. A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor

5. 6.9 A 1.1µm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based analog-to-digital converters

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