An On-chip Layer-wise Training Method for RRAM based Computing-in-memory Chips-Reference-Cited by-同舟云学术

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An On-chip Layer-wise Training Method for RRAM based Computing-in-memory Chips

Published:2021-02-01 Issue: Volume: Page:
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Container-title:2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
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Author:

Geng Yiwen,Gao Bin,Zhang Qingtian,Zhang Wenqiang,Yao Peng,Xi Yue,Lin Yudeng,Chen Junren,Tang Jianshi,Wu Huaqiang,Qian He

Funder

NSFC

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9473901/9473226/09473931.pdf?arnumber=9473931

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Mitigate IR-Drop Effect by Modulating Neuron Activation Functions for Implementing Neural Networks on Memristor Crossbar Arrays;IEEE Electron Device Letters;2023-08

2. Binary Synaptic Array for Inference and Training with Built-in RRAM Electroforming Circuit;2023 24th International Symposium on Quality Electronic Design (ISQED);2023-04-05

3. Variation Tolerant RRAM Based Synaptic Architecture for On-Chip Training;IEEE Transactions on Nanotechnology;2023

4. Write or not;Proceedings of the 59th ACM/IEEE Design Automation Conference;2022-07-10

5. Toward memristive in-memory computing: principles and applications;Frontiers of Optoelectronics;2022-05-12

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