1. Towards Analysing Cache-Related Preemption Delay in Non-Inclusive Cache Hierarchies;ACM Transactions on Embedded Computing Systems;2024-09-10
2. CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-06
3. Atalanta: Open-Source RISC-V Microcontroller for Rust-Based Hard Real-Time Systems;Lecture Notes in Computer Science;2024
4. Design of High Reliability Debugging System for RISC- V Microprocessor;2023 3rd International Conference on Electrical Engineering and Control Science (IC2ECS);2023-12-29
5. ENEST - Efficient Interrupt Nesting for RISC-V based CPUs;2023 IEEE 2nd Industrial Electronics Society Annual On-Line Conference (ONCON);2023-12-08