A 24-GHz 65-nm CMOS 3-D Radial and Vertically Stacked Transmitter Front-End IC for Vital-sign Detection Radar Applications-Reference-Cited by-同舟云学术

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A 24-GHz 65-nm CMOS 3-D Radial and Vertically Stacked Transmitter Front-End IC for Vital-sign Detection Radar Applications

Published:2022-11-29 Issue: Volume: Page:
ISSN:
Container-title:2022 Asia-Pacific Microwave Conference (APMC)
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Author:

Lin Yi-Hsien¹,Chao Ti-Yu¹,Hsiao Shao-Cheng¹,Huang Yen-Ju¹,Liang You-Jen¹,Tsai Jeng-Han²,Alsuraisry Hamed³,Huang Tian-Wei¹

Affiliation:

1. National Taiwan University,Department of Electrical Engineering & Graduate Institute of Communication Engineering,Taipei,Taiwan

2. National Taiwan Normal University,Department of Electrical Engineering,Taipei,Taiwan

3. King Abdulaziz City for Science and Technology (KACST),Riyadh,Saudi Arabia

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9999720/9999721/09999843.pdf?arnumber=9999843

Reference9 articles.

1. A 60-GHz Power Amplifier Design Using Dual-Radial Symmetric Architecture in 90-nm Low-Power CMOS

2. A Broadband MFCW Agile Radar Concept for Vital-Sign Detection Under Various Thoracic Movements

3. Design of a 5.2-GHz CMOS Power Amplifier Using TF-Based 2-Stage Dual-Radial Power Splitting/Combining Architecture

4. MMW Ultra-Compact ${\rm N}$-Way Transformer PAs Using Bowtie-Radial Architecture in 65-nm CMOS

5. A 0.7-mW V-Band Transformer-Based Positive- Feedback Receiver Front-End in a 65-nm CMOS

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