Reliability-aware design of metal/high-k gate stack for high-performance SiC power MOSFET-Reference-Cited by-同舟云学术

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Reliability-aware design of metal/high-k gate stack for high-performance SiC power MOSFET

Published:2017-05 Issue: Volume: Page:
ISSN:
Container-title:2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)
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Author:

Hosoi Takuji,Azumo Shuji,Kashiwagi Yusaku,Hosaka Shigetoshi,Yamamoto Kenji,Aketa Masatoshi,Asahara Hirokazu,Nakamura Takashi,Kimoto Tsunenobu,Shimura Takayoshi,Watanabe Heiji

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7981281/7988866/07988906.pdf?arnumber=7988906

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Investigation on Switching Characteristics of 3.3kV SiC Power MOSFETs with SiO<sub>2</sub>/ SiN Gate Stack;Materials Science Forum;2023-06-05

2. Outlook for Dielectric/SiC Interfaces for Future Generation MOSFETs;Materials Science Forum;2023-05-31

3. Recent Developments and Prospects of Fully Recessed MIS Gate Structures for GaN on Si Power Transistors;Energies;2023-03-24

4. On-Resistance–Reliability Tradeoffs in Al₂O₃/LaAlO₃/SiO₂ Gate for SiC Power MOSFETs;IEEE Transactions on Electron Devices;2023-02

5. Verification of Single-Pulse Avalanche Failure Mechanism for Double-Trench SiC Power MOSFETs;IEEE Journal of Emerging and Selected Topics in Power Electronics;2021-04

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