Improving Cell-Aware Test for Intra-Cell Short Defects
Author:
Affiliation:
1. Realtek Semiconductor Corporation,Taiwan
2. National Yang Ming Chiao Tung University,Department of Computer Science,Hsinchu,Taiwan
3. Institute of Electronics, National Yang Ming Chiao Tung University,Hsinchu,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9774496/9774497/09774502.pdf?arnumber=9774502
Reference20 articles.
1. Methodology of Generating Timing-Slack-Based Cell-Aware Tests
2. Embedded deterministic test points for compact cell-aware tests
3. Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test
4. Cell-aware test generation time reduction by using switch-level ATPG
5. Defect-Location Identification for Cell-Aware Test
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1. A comparative overview of ATPG flows targeting traditional and cell-aware fault models;2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2022-10-24
2. Recent Trends and Perspectives on Defect-Oriented Testing;2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS);2022-09-12
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