Modeling Oxide Regrowth During Selective Etching in Vertical 3D NAND Structures
Author:
Affiliation:
1. Institute for Microelectronics, TU Wien,Christian Doppler Laboratory for Multi-Scale Process Modeling of Semiconductor Devices and Sensors,Vienna,Austria,1040
2. St Ives,Silvaco Europe Ltd.,Cambridgeshire,United Kingdom,PE27 5JL
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10319472/10319477/10319506.pdf?arnumber=10319506
Reference12 articles.
1. Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory;jang;Proc IEEE VLSI Technol Symp,2009
2. Redeposition mechanism on silicon oxide layers during selective etching process in 3D NAND manufacture
3. Level Set Methods and Dynamic Implicit Surfaces;ohser;Appl Math Ser,2003
4. Process Improvements for 7th Generation 1Tb Quad-Level Cell 3D NAND Flash Memory in Mass Production
5. Selective wet etching of Si3N4/SiO2 in phosphoric acid with the addition of fluoride and silicic compounds
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