Modeling Degradation and Breakdown in SiO<sub>2</sub> and High-k Gate Dielectrics-Reference-Cited by-同舟云学术

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Modeling Degradation and Breakdown in SiO₂ and High-k Gate Dielectrics

Published:2023-09-27 Issue: Volume: Page:
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Container-title:2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
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Author:

Padovani Andrea¹,Torraca Paolo La²,Larcher Luca³,Strand Jack⁴,Shluger Alexander⁴

Affiliation:

1. University of Modena and Reggio Emilia,Engineering Department "Enzo Ferrari" (DIEF),Reggio Emilia,Italy

2. University of Modena and Reggio Emilia,Department of Sciences and Methods for Engineering (DISMI),Reggio Emilia,Italy

3. Applied Materials,MDLx Italy,Reggio Emilia,Italy

4. University of College London,Department of Physics and Astronomy,London,UK

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10319472/10319477/10319608.pdf?arnumber=10319608

Reference46 articles.

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