When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic Computing
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/9112295/9116186/09116390.pdf?arnumber=9116390
Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Not your father’s stochastic computing (SC)! Efficient yet Accurate End-to-End SC Accelerator Design;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24
2. Efficient Non-Linear Adder for Stochastic Computing with Approximate Spatial-Temporal Sorting Network;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09
3. Low-Complexity Precision-Scalable Multiply-Accumulate Unit Architectures for Deep Neural Network Accelerators;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-04
4. Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04
5. Fault-Tolerant Deep Learning Processors;Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design;2023
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