PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs

Author:

Lin Zhe1,Yuan Zike2,Zhao Jieru3,Zhang Wei4,Wang Hui1,Tian Yonghong1

Affiliation:

1. Peng Cheng Laboratory,China

2. The University of Auckland,New Zealand

3. Shanghai Jiao Tong University,China

4. The Hong Kong University of Science and Technology,Hong Kong, China

Publisher

IEEE

Reference20 articles.

1. Vivado design suite tutorial: Power Analysis and Optimization;Xilinx White Paper,2019

2. UltraScale Architecture Low Power Technology Overview;kolluri;Xilinx White Paper,2015

3. Accurate operation delay prediction for FPGA HLS using graph neural networks

4. Semi-supervised classification with graph convolutional networks;kipf;Proc of ICLR,0

5. Inductive representation learning on large graphs;hamilton;Proc of NeurIPS,0

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1. HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond;Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD;2024-09-09

2. Hard SyDR: A Benchmarking Environment for Global Navigation Satellite System Algorithms;Sensors;2024-01-09

3. Power Analysis;FPGA EDA;2024

4. HGBO-DSE: Hierarchical GNN and Bayesian Optimization based HLS Design Space Exploration;2023 International Conference on Field Programmable Technology (ICFPT);2023-12-12

5. HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis;2023 IEEE 34th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2023-07

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