Error-Control Coding Algorithms and Architecture for Modern Applications Powered by LDPC Codes and Belief Propagation

Author:

Pal Prashnatita1,Sahana Bikash Chandra1,Poray Jayanta2,Bal Aditi3

Affiliation:

1. National Institute Of Technology, Patna,Dept. of Electronics & Communication Engineering,Patna,India

2. Techno India University,Dept. of Computer Sc. & Engineering,Kolkata,West Bengal,India

3. St. Thomas' College of Engineering & Technology,Dept. of Information Technology,India

Publisher

IEEE

Reference18 articles.

1. Mapping Interleaving Laws to Parallel Turbo and LDPC Decoder Architectures

2. Low Complexity LDPC Code Decoders for Next Generation Standards

3. A systematic approach for achieving low bit error rate of LDPC decoder using MWD algorithm;shruti;International Conference on Wireless Communications Signal Processing and Networking (WiSPNET),0

4. Block-LDPC: a practical LDPC coding system design approach

5. RSA encrypted FSK RF transmission powered by an innovative microwave technique for invulnerable security

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