HADAS: Hardware-Aware Dynamic Neural Architecture Search for Edge Performance Scaling
Author:
Affiliation:
1. LAMIH/UMR CNRS, Université Polytechnique Hauts-de-France,Valenciennes,France
2. University of California,Department of Electrical Engineering and Computer Science,Irvine,USA
Funder
National Science Foundation (NSF)
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10136870/10136706/10137095.pdf?arnumber=10137095
Reference16 articles.
1. EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference
2. A Novel Design of Adaptive and Hierarchical Convolutional Neural Networks using Partial Reconfiguration on FPGA
3. Once-for-all: Train one network and specialize it for efficient deployment;cai;ArXiv Preprint,2019
4. Predictive exit: Prediction of fine-grained early exits for computation-and energy-efficient inference;li;ArXiv Preprint,2022
5. Hardware-Software Co-design Approach for Deep Learning Inference
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