ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training
Author:
Affiliation:
1. Northeastern University,Boston,USA
2. Simon Fraser University,Burnaby,Canada
Funder
NSF
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10136870/10136706/10137222.pdf?arnumber=10137222
Reference25 articles.
1. Stochastic Rounding: Algorithms and Hardware Accelerator
2. Towards efficient deep neural network training by FPGA-based batch-level parallelism
3. Low-precision floating-point schemes for neural network training;ortiz;ArXiv Preprint,2018
4. On-chip training of recurrent neural networks with limited numerical precision
5. Imagenet classification with deep convolutional neural networks;krizhevsky;NIPS,2012
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