AIrchitect: Automating Hardware Architecture and Mapping Optimization

Author:

Samajdar Ananda1,Joseph Jan Moritz2,Krishna Tushar3

Affiliation:

1. Georgia Tech / IBM Research

2. RWTH Aachen,Aachen,Germany

3. Georgia Tech,Atlanta,GA,USA

Funder

NSF

Publisher

IEEE

Reference15 articles.

1. Scale-sim: Systolic CNN Accelerator Simulator;samajdar;ArXiv Preprint,2018

2. ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators

3. Apollo: Transferable architecture exploration;yazdanbakhsh;ArXiv Preprint,2021

4. A Systematic Methodology for Characterizing Scalability of DNN Accelerators using Scale-Sim;ISPASS,2020

5. Accurate and efficient regression modeling for microarchitectural performance and power prediction

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