A Design of 2-Stage Voltage Ramp-Up SRAM Physical Unclonable Function
Author:
Affiliation:
1. School of Nano-Tech and Nano-Bionics, University of Science and Technology of China,Hefei,China,230026
2. Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences,Suzhou,China,215123
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/9970761/10488048/10488070.pdf?arnumber=10488070
Reference36 articles.
1. 13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS
2. Voltage Over-Scaling-Based Lightweight Authentication for IoT Security
3. Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT
4. A Highly Reliable Arbiter PUF With Improved Uniqueness in FPGA Implementation Using Bit-Self-Test
5. A Novel Ultra-Compact FPGA-compatible TRNG Architecture exploiting Latched Ring Oscillators
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