1. Goryashko A.P. Sintez diagnostiruemyh skhem vychislitel'nyh ustrojstv [Synthesis diagnosed circuits computing devices] / A.P. Goryashko. -M.: Nauka [The science], 1987, p. 288;
2. Brglez F., "On Testability Analysis of Combinational Networks," in Proc. of the International Symp. on Circuits and Systems, May 1984, pp. 220 -225;
3. Khade R., Gourkar S. "Fault Testing of CMOS Integrated Circuits Using Signature Analysis Method," International Journal of Application or Innovation in Engineering & Management (IJAIEM), Vol. 2, Issue 5, May 2013, pp. 73-82;
4. Litikov I.P. Kol'cevoe testirovanie cifrovyh ustrojstv [Circuit testing of digital devices]/ I.P. Litikov.-M.: Energoatomisdat, 1990. p.157;
5. Goessel M., Chakrabarty K., Ocheretnij V. "A Signature Analysis Technique for the Identifi cation of Failing Vectors with Application to Scan-BIST," Journal of Electronic Testing: Theory and Applications, vol. 20, 2004, pp. 611-622;